View NLSX5011MUTCG_4878156.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

NLSX5011 1-Bit 100 Mb/s Configurable Dual-Supply Level Translator
The NLSX5011 is a 1-bit configurable dual-supply autosensing bidirectional level translator that does not require a direction control pin. The I/O VCC- and I/O VL-ports are designed to track two different power supply rails, VCC and VL respectively. Both the VCC and the VL supply rails are configurable from 0.9 V to 4.5 V. This allows a logic signal on the VL side to be translated to either a higher or a lower logic signal voltage on the VCC side, and vice-versa. The NLSX5011 offers the feature that the values of the VCC and VL supplies are independent. Design flexibility is maximized because VL can be set to a value either greater than or less than the VCC supply. In contrast, the majority of competitive auto sense translators have a restriction that the value of the VL supply must be equal to less than (VCC - 0.4) V. The NLSX5011 has high output current capability, which allows the translator to drive high capacitive loads such as most high frequency EMI filters. Another feature of the NLSX5011 is that each I/O_VLn and I/O_VCCn channel can function as either an input or an output. An Output Enable (EN) input is available to reduce the power consumption. The EN pin can be used to disable both I/O ports by putting them in 3-state which significantly reduces the supply current from both VCC and VL. The EN signal is referenced to the VL supply.
Features http://onsemi.com MARKING DIAGRAMS
UDFN6 MU SUFFIX CASE 517AA 1 P M G = Specific Device Code = Date Code = Pb-Free Package ULLGA6 AMX1 SUFFIX CASE 613AE AJ M G = Specific Device Code = Date Code = Pb-Free Package M G P
AJ M G
1
* Wide VCC, VL Operating Range: 0.9 V to 4.5 V * VL and VCC are independent
1 E M G
- VL may be greater than, equal to, or less than VCC
= Specific Device Code = Date Code = Pb-Free Package
* High 100 pF Capacitive Drive Capability * High-Speed with 140 Mb/s Guaranteed Date Rate * * * * * *
for VCC, VL > 1.8 V Low Bit-to-Bit Skew Overvoltage Tolerant Enable and I/O Pins Non-preferential Power-Up Sequencing Power-Off Protection Small packaging: ULLGA6 & UDFN6 Packages These are Pb-Free Devices
ORDERING INFORMATION
Device NLSX5011MUTCG NLSX5011AMX1TCG NLSX5011BMX1TCG Package UDFN6 (Pb-Free) ULLGA6 (Pb-Free) ULLGA6 (Pb-Free) Shipping 3000/T ape & Reel 3000/T ape & Reel 3000/T ape & Reel
Typical Applications
* Mobile Phones, PDAs, Other Portable Devices
Important Information
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
* ESD Protection for All Pins:
HBM (Human Body Model) > 8000 V
(c) Semiconductor Components Industries, LLC, 2010
July, 2010 - Rev. 0
1
Publication Order Number: NLSX5011/D
E
ULLGA6 BMX1 SUFFIX CASE 613AF
M G
NLSX5011
VL +1.8V +3.6V P One-Shot R1 N One-Shot +3.6 V System I/O VL I/O VCC VCC
VL +1.8 V System
NLSX5011
VCC
I/O1 I/On GND OE
I/O VL1
I/O VCC1
I/O1 I/On GND
P One-Shot R2
I/O VLn I/O VCCn EN GND
N One-Shot
Figure 1. Typical Application Circuit
Figure 2. Simplified Functional Diagram (1 I/O Line)
2.5 V
3.0 V
2.5 V
1.8 V
mC
VL
NLSX5011
VCC
Peripheral
mC
VL
NLSX5011
VCC
Peripheral
GPIO
I/O VL1
I/O VCC1
EN
GPIO
I/O VL1
I/O VCC1
EN
ANO
EN
GND
ANO
EN
GND
Figure 3. Application Example for VL < VCC
Figure 4. Application Example for VL > VCC
http://onsemi.com
2
NLSX5011
VL GND I/O VL I/O VL I/O VCC 1 2 3 8 7 6 VCC EN I/O VCC
EN
VL
VCC GND
ULLGA6/UDFN6 (Top View)
Figure 5. Logic Diagram PIN ASSIGNMENT
Pins VCC VL GND EN I/O VCCn I/O VLn Description VCC Input Voltage VL Input Voltage Ground Output Enable I/O Port, Referenced to VCC I/O Port, Referenced to VL
Figure 6. Pin Assignments FUNCTION TABLE
EN L H Operating Mode Hi-Z I/O Buses Connected
MAXIMUM RATINGS
Symbol VCC VL I/O VCC I/O VL VI IIK IOK ICC IL IGND TSTG Parameter High-side DC Supply Voltage Low-side DC Supply Voltage VCC-Referenced DC Input/Output Voltage VL-Referenced DC Input/Output Voltage Enable Control Pin DC Input Voltage DC Input Diode Current DC Output Diode Current DC Supply Current Through VCC DC Supply Current Through VL DC Ground Current Through Ground Pin Storage Temperature Value -0.5 to +5.5 -0.5 to +5.5 -0.5 to +5.5 -0.5 to +5.5 -0.5 to +5.5 -50 -50 $100 $100 $100 -65 to +150 VI < GND VO < GND Condition Unit V V V V V mA mA mA mA mA C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VL VI VIO TA Dt/DV Parameter High-side Positive DC Supply Voltage Low-side Positive DC Supply Voltage Enable Control Pin Voltage Bus Input/Output Voltage Operating Temperature Range Input Transition Rise or Rate VI, VIO from 30% to 70% of VCC; VCC = 3.3 V $ 0.3 V I/O VCC I/O VL Min 0.9 0.9 GND GND GND -40 0 Max 4.5 4.5 4.5 4.5 4.5 +85 10 Unit V V V V C ns
http://onsemi.com
3
NLSX5011
DC ELECTRICAL CHARACTERISTICS
-405C to +855C Symbol VIHC VILC VIHL VILL VIH VIL VOHC VOLC VOHL VOLL IQVCC Parameter I/O VCC Input HIGH Voltage I/O VCC Input LOW Voltage I/O VL Input HIGH Voltage I/O VL Input LOW Voltage Control Pin Input HIGH Voltage Control Pin Input LOW Voltage I/O VCC Output HIGH Voltage I/O VCC Output LOW Voltage I/O VL Output HIGH Voltage I/O VL Output LOW Voltage VCC Supply Current TA = +25C TA = +25C I/O VCC source current = 20 mA I/O VCC sink current = 20 mA I/O VL source current = 20 mA I/O VL sink current = 20 mA EN = VL, IO = 0 A, (I/O VCC = 0 V or VCC, I/O VL = float) or (I/O VCC = float, I/O VL = 0 V or VL) TA = +25C, EN = 0 V (I/O VCC = 0 V or VCC, I/O VL = float) or (I/O VCC = float, I/O VL = 0 V or VL) TA = +25C, EN = 0V TA = +25C I/O VCC = 0 to 4.5V, I/O VL = 0 to 4.5 V 1. 2. 3. 4. Test Conditions (Note 1) VCC (V) (Note 2) 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 VL (V) (Note 3) 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 Min 2/3 * VCC - 2/3 * VL - 2/3 * VL - 0.9 * VCC - 0.9 * VL - - Typ (Note 4) - - - - - - - - - - - Max - 1/3 * VCC - 1/3 * VL - 1/3 * VL - 0.2 - 0.2 1 -555C to +1255C Min 2/3 * VCC - 2/3 * VL - 2/3 * VL - 0.9 * VCC - 0.9 * VL - - Max - 1/3 * VCC - 1/3 * VL - 1/3 * VL - 0.2 - 0.2 2.5 Unit V V V V V V V V V V mA
IQVL ITS-VCC
VL Supply Current VCC Tristate Output Mode Supply Current VL Tristate Output Mode Supply Current I/O Tristate Output Mode Leakage Current Control Pin Input Current Power Off Leakage Current
0.9 - 4.5 0.9 - 4.5
0.9 - 4.5 0.9 - 4.5
- -
- -
1 0.5
- -
2.5 1.5
mA mA
ITS-VL
0.9 - 4.5
0.9 - 4.5
-
-
0.5
-
1.5
mA
IOZ II IOFF
0.9 - 4.5 0.9 - 4.5 0 0.9 - 4.5 0
0.9 - 4.5 0.9 - 4.5 0 0 0.9 - 4.5
- - - - -
- - - - -
1 1 1 1 1
- - - - -
1.5 1 1.5 1.5 1.5
mA mA mA
Normal test conditions are VI = 0 V, CIOVCC 15 pF and CIOVL 15 pF, unless otherwise specified. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
http://onsemi.com
4
NLSX5011
TIMING CHARACTERISTICS
-555C to +1255C Symbol tR-VCC tF-VCC tR-VL tF-VL ZOVCC Parameter I/O VCC Rise Time I/O VCC Fall Time I/O VL Rise Time I/O VL Fall Time I/O VCC One-Shot Output Impedance I/O VL One-Shot Output Impedance Test Conditions (Note 5) CIOVCC = 15 pF CIOVCC = 15 pF CIOVL = 15 pF CIOVL = 15 pF (Note 9) VCC (V) (Note 6) 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 1.8 4.5 0.9 1.8 4.5 0.9 - 4.5 1.8 - 4.5 CIOVCC = 30 pF CIOVCC = 50 pF CIOVCC = 100 pF tPD_VCC-VL Propagation Delay (Driving I/O VL) CIOVL = 15 pF CIOVL = 30 pF CIOVL = 50 pF CIOVL = 100 pF tSK IIN_PEAK Channel-to-Channel Skew Input Driver Maximum Peak Current CIOVCC = 15 pF, CIOVL = 15 pF (Note 9) EN = VL; I/O_VCC = 1 MHz Square Wave, Amplitude = VCC, or I/O_VL = 1 MHz Square Wave, Amplitude = VL (Note 9) 0.9 - 4.5 1.8 - 4.5 1.0 - 4.5 1.8 - 4.5 1.2 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 1.0 - 4.5 1.8 - 4.5 1.2 - 4.5 1.8 - 4.5 0.9 - 4.5 0.9 - 4.5 VL (V) (Note 7) 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 Min - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Typ (Note 8) - - - - - - - - 37 20 6.0 37 20 6.0 - - - - - - - - - - - - - - - - - - Max 8.5 3.5 8.5 3.5 8.5 3.5 8.5 3.5 - - - - - - 35 10 35 10 37 11 40 13 35 10 35 10 37 11 40 13 0.15 5.0 nS mA nS W nS nS nS Unit nS
ZOVL
(Note 9)
0.9 - 4.5
W
tPD_VL-VCC Propagation Delay (Driving I/O VCC)
CIOVCC = 15 pF
0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 1.0 - 4.5 1.8 - 4.5 1.2 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 1.0 - 4.5 1.8 - 4.5 1.2 - 4.5 1.8 - 4.5 0.9 - 4.5 0.9 - 4.5
nS
5. 6. 7. 8.
Normal test conditions are VI = 0 V, CIOVCC 15 pF and CIOVL 15 pF, unless otherwise specified. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design. 9. Guaranteed by design.
http://onsemi.com
5
NLSX5011
TIMING CHARACTERISTICS (continued)
-555C to +1255C Symbol tEN-VCC Parameter I/O_VCC Output Enable Time tPZH tPZL tEN-VL I/O_VL Output Enable Time tPZH tPZL tDIS-VCC I/O_VCC Output Disable Time tPHZ tPLZ tDIS-VL I/O_VL Output Disable Time tPHZ tPLZ MDR Maximum Data Rate Test Conditions (Note 10) CIOVCC = 15 pF, I/O_VL = VL CIOVCC = 15 pF, I/O_VL = 0 V CIOVL = 15 pF, I/O_VCC = VCC CIOVL = 15 pF, I/O_VCC = 0 V CIOVCC = 15 pF, I/O_VL = VL CIOVCC = 15 pF, I/O_VL = 0 V CIOVL = 15 pF, I/O_VCC = VCC CIOVL = 15 pF, I/O_VCC = 0 V CIO = 15 pF CIO = 30 pF CIO = 50 pF CIO = 100 pF VCC (V) (Note 11) 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 1.0 - 4.5 1.8 - 4.5 1.2 - 4.5 1.8 - 4.5 VL (V) (Note 12) 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 0.9 - 4.5 1.8 - 4.5 0.9 - 4.5 1.8 - 4.5 1.0 - 4.5 1.8 - 4.5 1.2 - 4.5 1.8 - 4.5 Min - - - - - - - - 50 140 40 120 30 100 20 60 Typ (Note 13) - - - - - - - - - - - - - - - - Max 160 130 160 130 210 175 210 175 - - - - - - - - mbps nS nS nS Unit nS
10. Normal test conditions are VI = 0 V, CIOVCC 15 pF and CIOVL 15 pF, unless otherwise specified. 11. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 12. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 13. Typical values are for VCC = +2.8 V, VL = +1.8 V and TA = +25C. All units are production tested at TA = +25C. Limits over the operating temperature range are guaranteed by design.
http://onsemi.com
6
NLSX5011
DYNAMIC POWER CONSUMPTION (TA = +25C)
Symbol CPD_VL Parameter VL = Input port, VCC = Output Port Test Conditions CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) VCC (V) (Note 14) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 CPD_VCC VL = Input port, VCC = Output Port CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = VL (outputs enabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VL (V) (Note 15) 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 Typ (Note 16) 39 20 17 14 13 14 13 19 37 30 29 29 29 30 29 19 29 29 29 29 29 30 29 35 21 18 18 14 13 14 13 30 pF pF pF Unit pF
14. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 15. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 16. Typical values are at TA = +25C. 17. CPD VL and CPD VCC are defined as the value of the IC's equivalent capacitance from which the operating current can be calculated for the VL and VCC power supplies, respectively. ICC = ICC (dynamic) + ICC (static) ICC(operating) CPD x VCC x fIN x NSW where ICC = ICC_VCC + ICC VL and NSW = total number of outputs switching.
http://onsemi.com
7
NLSX5011
STATIC POWER CONSUMPTION (TA = +25C)
Symbol CPD_VL Parameter VL = Input port, VCC = Output Port Test Conditions CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) VCC (V) (Note 18) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 CPD_VCC VL = Input port, VCC = Output Port CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VCC = Input port, VL = Output Port CLoad = 0, f = 1 MHz, EN = GND (outputs disabled) 0.9 1.5 1.8 1.8 1.8 2.5 2.8 4.5 VL (V) (Note 19) 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 4.5 1.8 1.5 1.8 2.8 2.5 1.8 0.9 Typ (Note 20) 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 0.01 pF pF pF Unit pF
18. VCC is the supply voltage associated with the I/O VCC port, and VCC ranges from +0.9 V to 4.5 V under normal operating conditions. 19. VL is the supply voltage associated with the I/O VL port, and VL ranges from +0.9 V to 4.5 V under normal operating conditions. 20. Typical values are at TA = +25C
http://onsemi.com
8
NLSX5011
VL EN Source I/O VL I/O VCC CIOVCC I/O VL CIOVL Source I/O VL 90% 50% 10% tPD_VL-VCC I/O VCC 90% 50% 10% tF-VCC tR-VCC tRISE/FALL v 3 ns I/O VCC 90% 50% 10% tPD_VL-VCC tPD_VCC-VL I/O VL 90% 50% 10% tF-VL tR-VL tPD_VCC-VL tRISE/FALL v 3 ns NLSX5011 VCC VL EN I/O VCC NLSX5011 VCC
Figure 7. Driving I/O VL Test Circuit and Timing
Figure 8. Driving I/O VCC Test Circuit and Timing
VCC R1 CL RL 2xVCC OPEN
PULSE GENERATOR RT
DUT
Test tPZH, tPHZ tPZL, tPLZ
Switch Open 2 x VCC
CL = 15 pF or equivalent (Includes jig and probe capacitance) RL = R1 = 50 kW or equivalent RT = ZOUT of pulse generator (typically 50 W)
Figure 9. Test Circuit for Enable/Disable Time Measurement
tR Input tPLH Output 90% 50% 10% 90% 50% 10% tR tPHL tF 50% VL GND HIGH IMPEDANCE 10% 90% VOL VOH HIGH IMPEDANCE
VCC GND
EN
tPZL Output 50% tPZH Output 50%
tPLZ
tF
tPHZ
Figure 10. Timing Definitions for Propagation Delays and Enable/Disable Measurement
http://onsemi.com
9
NLSX5011
IMPORTANT APPLICATIONS INFORMATION
Level Translator Architecture
The NLSX5011 auto-sense translator provides bi-directional logic voltage level shifting to transfer data in multiple supply voltage systems. These level translators have two supply voltages, VL and VCC, which set the logic levels on the input and output sides of the translator. When used to transfer data from the I/O VL to the I/O VCC ports, input signals referenced to the VL supply are translated to output signals with a logic level matched to VCC. In a similar manner, the I/O VCC to I/O VL translation shifts input signals with a logic level compatible to VCC to an output signal matched to VL. The NLSX5011 translator consists of bi-directional channels that independently determine the direction of the data flow without requiring a directional pin. One-shot circuits are used to detect the rising or falling input signals. In addition, the one-shots decrease the rise and fall times of the output signal for high-to-low and low-to-high transitions.
Input Driver Requirements
VL pins to a high impedance state. Normal translation operation occurs when the EN pin is equal to a logic high signal. The EN pin is referenced to the VL supply and has Over-Voltage Tolerant (OVT) protection.
Uni-Directional versus Bi-Directional Translation
The NLSX5011 translator can function as a non-inverting uni-directional translator. One advantage of using the translator as a uni-directional device is that each I/O pin can be configured as either an input or output. The configurable input or output feature is especially useful in applications such as SPI that use multiple uni-directional I/O lines to send data to and from a device. The flexible I/O port of the auto sense translator simplifies the trace connections on the PCB.
Power Supply Guidelines
Auto-sense translators such as the NLSX5011 have a wide bandwidth, but a relatively small DC output current rating. The high bandwidth of the bi-directional I/O circuit is used to quickly transform from an input to an output driver and vice versa. The I/O ports have a modest DC current output specification so that the output driver can be over driven when data is sent in the opposite direction. For proper operation, the input driver to the auto-sense translator should be capable of driving 2 mA of peak output current. The bi-directional configuration of the translator results in both input stages being active for a very short time period. Although the peak current from the input signal circuit is relatively large, the average current is small and consistent with a standard CMOS input stage.
Enable Input (EN)
The NLSX5011 translator has an Enable pin (EN) that provides tri-state operation at the I/O pins. Driving the Enable pin to a low logic level minimizes the power consumption of the device and drives the I/O VCC and I/O
The values of the VL and VCC supplies can be set to anywhere between 0.9 and 4.5 V. Design flexibility is maximized because VL may be either greater than or less than the VCC supply. In contrast, the majority of the competitive auto sense translators has a restriction that the value of the VL supply must be equal to less than (VCC - 0.4) V. The sequencing of the power supplies will not damage the device during power-up operation. In addition, the I/O VCC and I/O VL pins are in the high impedance state if either supply voltage is equal to 0 V. For optimal performance, 0.01 to 0.1 mF decoupling capacitors should be used on the VL and VCC power supply pins. Ceramic capacitors are a good design choice to filter and bypass any noise signals on the voltage lines to the ground plane of the PCB. The noise immunity will be maximized by placing the capacitors as close as possible to the supply and ground pins, along with minimizing the PCB connection traces. The NLSX5011 translators have a power down feature that provides design flexibility. The output ports are disabled when either power supply is off (VL or VCC = 0 V). This feature causes all of the I/O pins to be in the power saving high impedance state.
http://onsemi.com
10
NLSX5011
PACKAGE DIMENSIONS
UDFN6 1.2 x 1.0, 0.4P CASE 517AA-01 ISSUE C
EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 mm FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. DIM A A1 A3 b D E e L L1 L2 MILLIMETERS MIN MAX 0.45 0.55 0.00 0.05 0.127 REF 0.15 0.25 1.20 BSC 1.00 BSC 0.40 BSC 0.30 0.40 0.00 0.15 0.40 0.50
D
A B L1
PIN ONE REFERENCE 2X
0.10 C
2X
0.10 C
0.10 C
(A3) A
A1
10X
0.08 C
SIDE VIEW A1
5X 1 3
SEATING PLANE
C L
L2
6X
b 0.10 C A B 0.05 C
NOTE 3
6
4
e BOTTOM VIEW
http://onsemi.com
11
III III III
DETAIL B Side View (Optional) 0.40 PITCH
II II II
E
DETAIL A Bottom View (Optional)
EXPOSED Cu MOLD CMPD
TOP VIEW
A3
MOUNTING FOOTPRINT*
0.42
6X
0.22
6X
1.07
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
NLSX5011
PACKAGE DIMENSIONS
ULLGA6 1.2 x 1.0, 0.4P CASE 613AE-01 ISSUE A
D A B
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 SEATING PLANE MILLIMETERS MIN MAX --- 0.40 0.00 0.05 0.15 0.25 1.20 BSC 1.00 BSC 0.40 BSC 0.25 0.35 0.35 0.45
0.10 C
0.10 C 0.05 C
6X
0.05 C
L1
III III
1 6
PIN ONE REFERENCE
E
TOP VIEW
A SIDE VIEW A1 e
3
C
MOUNTING FOOTPRINT SOLDERMASK DEFINED*
0.49
5X
0.26
6X
5X
L
NOTE 4
1.24
4
0.53
6X
1
PKG OUTLINE
b 0.10 C A B 0.05 C
NOTE 3
0.40 PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
12
NLSX5011
PACKAGE DIMENSIONS
ULLGA6 1.45 x 1.0, 0.5P CASE 613AF-01 ISSUE A
NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.30 mm FROM THE TERMINAL TIP. 4. A MAXIMUM OF 0.05 PULL BACK OF THE PLATED TERMINAL FROM THE EDGE OF THE PACKAGE IS ALLOWED. DIM A A1 b D E e L L1 MILLIMETERS MIN MAX --- 0.40 0.00 0.05 0.15 0.25 1.45 BSC 1.00 BSC 0.50 BSC 0.25 0.35 0.30 0.40
D
A B
0.10 C 0.10 C 0.05 C
6X
0.05 C
L1
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your loca Sales Representative
III III
1 6
PIN ONE REFERENCE
E
TOP VIEW
A SIDE VIEW A1 e
3 SEATING PLANE
C
MOUNTING FOOTPRINT SOLDERMASK DEFINED*
0.49
5X
0.30
6X
5X
L
NOTE 4
1.24
4
6X
b 0.10 C A B 0.05 C
NOTE 3
0.53
1
PKG OUTLINE
0.50 PITCH
DIMENSIONS: MILLIMETERS
BOTTOM VIEW
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
13
NLSX5011/D

▲Up To Search▲

Price & Availability of NLSX5011MUTCG

	To Download NLSX5011MUTCG Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .